1. Field of the Invention
The present invention relates generally to semiconductor integrated circuits, and more specifically to an interconnect structure and method for forming the structure.
2. Description of the Prior Art
In CMOS integrated circuits, various conductive structures are doped with P-type or N-type impurities. In order to interconnect these structures, at some point a P-N junction must be formed where the P-type and N-type conductive structures come together. As is known in the art, this junction causes a voltage drop of approximately 0.7 volts when biased in the forward direction.
In contemporary high density, low voltage integrated circuits, such as high density SRAMs, the presence of such a P-N junction may interfere with proper operation of the circuit. This is especially true as operating voltages for these devices increasingly move from 5 volt supplies to 3.3 volt, and lower, supplies. For example, FIG. 1 illustrates a portion of a CMOS memory cell. The access transistors are not shown in FIG. 1; only the cross-coupled latch portion of the cell is illustrated.
Referring to FIG. 1, a portion of a prior art SRAM cell 10 is illustrated. Cell 10 includes P-channel transistors 12, 14, and N-channel transistors 16, 18. The gates of transistors 12 and 16 are connected together, and connected to a common electrical node 20. In a similar manner, the gates of transistors 14 and 18 are connected together, and in turn connected to a common electrical node 22. The access transistors (not shown) are connected to signal lines 24 and 26.
The P-channel transistors 12, 14 have heavily doped, P-type, source and drain regions. In a typical embodiment, the connection between the gates of transistors 14 and 18, and the drain of transistor 12 is made by a polycrystalline silicon signal line 28. This signal line 28 is doped N-type for conductivity, and a P-N diode 30 is formed at the point where the polycrystalline silicon signal line 28 contacts the heavily doped drain. In a similar manner, a polycrystalline silicon signal line 32 connects the gates of transistors 12 and 16 to the drain of transistor 14. A diode 34 is also formed at the junction between the N-type doped signal line 32 and the P-type drain of transistor 14.
In some respects, diodes 30 and 34 do not adversely affect the functioning of the SRAM cell 10. All current which flows through transistors 12 and 14 flows from Vcc toward ground. Thus, diodes 30 and 34 are always biased in the forward direction. In other words, the P-N junction contained in these diodes does not act as a block to the flow of current during normal operation of the device.
However, diodes 30 and 34 do cause a voltage drop, typically of approximately 0.7 volts. If Vcc were to have a value of 10 volts or more, this voltage drop would have little effect on the operation of the SRAM cell 10. However, in high density, low voltage integrated circuit parts Vcc is more typically 5 volts or 3.3 volts. At low voltages such as these the 0.7 volt drop across diodes 30 and 34 does have an adverse impact on operation of the SRAM cell 10.
The voltage drop across the diodes is a significant fraction of the total supply voltage. This means that noise margins will be greatly reduced because the full supply voltage cannot be applied across the cell. In addition, this relatively large voltage drop lowers the current available during switching, which slows down the operating speed of the cell.
It would therefor be desirable to provide an interconnect technique for integrated circuits which would eliminate the P-N junction formed when making an electrical connection between active elements on CMOS integrated circuits. It would be further desirable for such a technique to be suitable for use with CMOS SRAM memory circuits. Such an interconnect structure will preferably be easy to implement without additional circuit complexity, and will be compatible with semiconductor process flows widely used in the industry.